The present invention relates to an embedded dynamic random access memory (eDRAM) structure for an extremely thin semiconductor-on-insulator (SOI) substrates and methods of manufacturing the same.
Embedded dynamic random access memory (eDRAM) is a dynamic random access memory (DRAM) embedded in a logic circuit to function as a high density cache memory. The eDRAM provides comparable access time as static random access memory (SRAM) at a smaller device area per cell. Typically, eDRAM arrays are employed as a level-2 (L2) cache or level-3 (L3) cache in a processor to provide a high density memory in a processor core. Due to high performance and a compact size, eDRAM has become one of the most efficient means for continued performance of semiconductor logic circuits requiring embedded memory including processors and system-on-chip (SoC) devices.
Semiconductor-on-insulator (SOI) substrates are employed in the semiconductor industry for performance benefits due to reduced capacitive coupling between semiconductor devices and the bulk portion of the substrate provided by a buried insulator layer. High performance logic chips are frequently manufactured on an SOI substrate to provide enhanced performance over devices having comparable dimensions and manufactured on a bulk substrate. Extremely thin semiconductor-on-insulator (ETSOI) substrate refers to a substrate including an extremely thin semiconductor-on-insulator layer, which typically has a thickness less than 100 nm, and more typically less than 50 nm.
A conventional eDRAM cell employing a deep trench capacitor provides an electrical connection between the deep trench capacitor and a source of an access transistor via a conductive buried strap, which is “buried” underneath a portion of a shallow trench isolation structure. In the case of an ETSOI substrate, the limited thickness of the ETSOI layer presents a unique challenge. The ETSOI layer is too thin to accommodate reliable manufacturing of a buried strap underneath a portion of a shallow isolation trench structure. The thickness of the ETSOI layer limits the vertical range of contact between the buried strap and the source of the access transistor. Further, even moderate variations in the recess depth corresponding to a bottom surface of the buried strap or the recess depth corresponding to the top surface of the buried strap can lead to significant variations in the resistance of the electrical path between the source and the inner node of the deep trench. Nonetheless, controlled and limited resistance between the source of the access transistor and the inner node of the deep trench is necessary to provide high performance from an eDRAM cell.